Although AMD 2nd-gen EPYC Rome datacenter CPUs released back in August, we are still getting a steady stream of details about the innards of the chip and how it works on a granular level.
The latest details come courtesy of German site Hardwareluxx and take a deep dive into the Input/Output die on the AMD Rome CPU.
AMD EPYC Rome CPU’s 39.54 Billion Transistors
The headline is that the Rome chip uses no less than 39.54 billion transistors thanks to a nine die design known as a multi-chip-module, which tally up to 1008mm2.
The nine dies consist of a 416mm2 Input/Output die with 8.34 billion transistors connected to eight compute core dies via Infinity Fabric, measuring 74mmm2 and boasting 3.9 billion transistors each. Every compute core die has two compute core complexes that include four Zen 2 cores, each one has an L2 cache, and an L3 cache shared between them.
In comparison, the Input/Output die on the current Ryzen family is a comparatively small 125mm2 and only has 2.09 billion transistors. Of course, this comes with the territory and the performance requirements of server chips but highlights how AMD has packed considerable power into its Rome chips.
Looking a little closer at the Input/Output die itself, we see that SRAM and crossbar switch take center stage winged by PCIe Gen 4 interfaces on the sides, while to the north and south, we see four 72-bit DDR4 memory channels.
The PCIe interfaces are particularly interesting as they can offer up to 162 PCIe lanes with double the bandwidth thanks to Gen 4 tech, which lowers the need for the Infinity Fabric to rely on the bus to up the lane count for models that are set to join AMD’s family further down the line. It’s future planning in action.
We also get a look at the Zen 2 compute core die, the same used across AMD’s Ryzen, EPYC, and soon to be released third-generation Threadripper processors.
Final Word
In the case of the EPYC Rome chip, AMD is using different configurations based on core count, which means despite having eight compute core die, they won’t all necessarily be used. Take, for example, the 16 core version with only four enabled compute core dies, and each of these only using four cores or two cores per compute core complex.
With the EPYC Milan and EPYC Genoa already in the pipeline, AMD is set to innovate the design of its chiplets further using Zen 3 and Zen 4 core tech, and we imagine this will translate to a higher market share across the board.