AMD Inadvertently Leaks Fresh Details About Epyc Zen 3 Milan and Zen 4 Genoa Server CPUs

Epyc Zen 3 Milan and Zen 4 Genoa Server CPUs

AMD took to the stage at the HPC-AI Advisory Council conference last month and unveiled a host of new details about its upcoming next-gen EPYC processors. The presentation was briefly available for all to see via YouTube detailing AMD’s roadmap for its future Epyc products, but was rapidly removed. However, the news was already out in the open.

Much of the focus is building upon the firm foundations laid down by the Epyc Rome CPUs as AMD continues to make inroads into the server and data center market. AMD is aiming to provide significant performance boosts with each iteration rather than Intel’s strategy of minor improvements with each successive model.

So what do we know?

AMD Epyc Milan

AMD’s Zen 3-based Epyc Milan chips use 7nm+ node tech to bring about a boost to performance per watt that surpasses that of Intel’s 10nm Ice Lake-SP Xeon CPUs. Milan has a nine-die setup, one being an I/O, and the other eight compute dies. The core itself features shared 32 MB cache for each die, meaning all of them share the same cache allocation rather than a separate Compute Complex for each one. This differs from the existing branching into two four-core Compute Complexes and the 16 MB L3 cache assigned to reach.

As for specifics, the Epyc Milan features 64 cores and 128 threads, SP3 socket compatibility (meaning backward compatibility with existing platforms), a TDP ranging from 120 W to 225 W depending on the SKU, PCIe 4.0 interface, and DDR4 memory support. Although rumors of SMT4 implementation have done the rounds as of late, the new specifications suggest this may not be the case as AMD opts for two threads per core. The Epyc Milan is touted for release in 2020.

AMD Epyc Genoa

For the Epyc Genoa, AMD is using what is presumed to be 5 nm or 6 nm process node Zen 4 architecture. The Genoa will be SP5 socket compatible. AMD mentions ‘new capabilities’, which may refer to a PCIe 5.0 interface that should have twice the bandwidth of PCIe 4.0 on an x16 interface with a 128 Gbps speed, as well as forthcoming DDR5 support. Genoa is expected sometime in 2021.

The news further places AMD in an ideal position to take even more server market share away from Intel and puts them on a course to dominating that particular sector of the chip market.

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