For the past few years, we’ve seen a bit of a battle over process nodes. It’s something that AMD and Intel have been going head to head over for a while now.
However, what we know about process nodes could be turned on its head due to a new research paper which suggests we change the way we name nodes.
The paper was put together by nine authors coming from MIT, Berkeley, Stanford, and TSMC and is titled: “A Density Metric for Semiconductor Technology”.
What Does The Research Suggest?
The researchers suggest that we should change the way we standardize advances in semiconductor lithographic manufacturing.
The paper suggests that we ditch the transistor gate length (e.g. 7nm or 10nm) as a measure of quality and performance. They say we should be focusing on transistor density instead.
Interestingly, this is the route that Intel has been proposing for years but now a researcher from TSMC has lent support for this idea.
How Does The Industry Currently Name Process Nodes?
To understand the problem, it’s important to look at the way the industry currently names process nodes. You’ll have no doubt already heard about 14nm, 12nm, 10nm, and 7nm because of their appearance in AMD and Intel chips. We’ve always been told that the smaller this number, the better. However, technology has moved on and those names may no longer be appropriate.
With every company approaching this industry slightly differently, the way we used to standardize technology is changing. It’s come to a point where the names on process nodes are more of a marketing decision than a technical term.
“Driven by competitive marketing in the most recent decade, this label has become decoupled from, and can be several times smaller than, the actual minimum gate length, while it also fails to convey other essential characteristics of the technology,” the researchers say in this paper.
This echoes the argument put forward by Mark Bohr in 2017 from Intel. He suggested that it was becoming increasingly difficult to scale and name process nodes accurately and that changes needed to be applied to the whole industry.
“Some companies have abandoned this rule, yet continued to advance node names, even in cases where there was minimal or no density increase. The result is that node names have become a poor indicator of where a process stands on the Moore’s Law curve.”
The Current Naming Process Could Become Obsolete Soon
Another thing to consider is what happens when the names dip below 1nm? We already know that TSMC is working on a 2nm process node so it looks like we’ll reach that problem far sooner than previously thought.
This means the suggestion that we should measure advancement by density could be the change we need right now before everything gets way too confusing.
The paper also states: “Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits.”
How Could We Measure Process Nodes in the Future?
The method suggested by the research paper involves something called the Logic, Memory, Connectivity Metric (LMC).
This would substitute a single transistor length for a three-part number instead. This number would consist of DL (density of logic transistors), DM (density of main memory), and DC (density of connections between main memory and logic) values.
This would result in a type of system measurement formula rather than a straightforward measure of the lithographic processes that we’re used to seeing.
The researchers say that this would lead to a more accurate way to measure and compare process nodes.
The solution put forward by Mark Bohr was that we could measure the density of 2-input NAND cells and scan flip flop cells which would create a single transistor/mm2 measurement. However, this doesn’t account for SRAM cell size so Intel suggests using a separate measurement alongside logic density as well.
Why Is Intel Keen to Change This Process?
Intel typically leads the way when it comes to transistor density. For its 10nm process, Intel reports a density of 100.76 MTr/mm2 whereas TSMC reports 91.2 MTr/mm2 for its 7nm process.
How this could potentially change the industry would be interesting to see, particularly in regards to the competition between Intel and AMD.
It’s probably going to be hard to convince the entire industry to agree to a universal density metric. However, with Intel onboard and this research paper coming from someone at TSMC, perhaps the argument is closer to becoming a reality than we might think.